With miniaturization in a recent semiconductor manufacturing technique, the number of transistors forming a large scale integrated (LSI) circuit has increased. Particularly in a system LSI circuit, a required memory capacity has increased with complication and enlargement of components. Thus, it has been important that a method for efficiently mounting a system LSI circuit including a large-capacity memory is realized, considering a cost.
Meanwhile, a wire bonding method or a flip-chip method has been typically used as a method for connecting an LSI circuit and a package together. If such mounting methods are used, it is required that a memory is mounted in a chip of the system LSI circuit, on a chip mounted substrate, or on a mounting substrate. It is likely to result in, e.g., limitations on capacity of the memory to be mounted, an increase in mounting area on the substrate, and an increase in mounting cost.
A chip-on-chip (COC) structure is employed as one of techniques for the foregoing situation.
FIG. 12 illustrates a cross-sectional view of a typical COC structure. Referring to FIG. 12, a chip 101 and a chip 102 are electrically connected together through bumps 104. Each bump 104 is provided on a corresponding one of a plurality of pads (not shown in the figure) each provided on the chip 101 or the chip 102. A space between the chip 101 and the chip 102 is filled with underfill resin 105. The chip 101 includes pads (not shown in the figure) for wire bonding, and is connected to a substrate 103 through each wire 106 provided on a corresponding one of the pads for wire bonding. The chip 101, the chip 102, and the wires 106 are covered by mold resin 107 (only an outer shape thereof is indicated by a dashed line).
As described above, the COC structure allows the plurality of chips to be stacked and mounted on the substrate 103, and therefore the chips can be more efficiently bonded together within a smaller area as compared to the conventional wire bonding method and flip-chip method.
If the lower chip 101 has, referring to FIG. 13, a smaller area in the COC structure, a region enough for wire bonding cannot be formed. Moreover, when the bumps 104 are placed so as to be concentrated at the center of the chip, if the chip 101 and the chip 102 are stacked on each other, the upper chip 102 becomes unstable, and therefore parallelism of the upper chip 102 cannot be maintained.
External stress is applied to an inside of the LSI circuit (chip) through the pads placed on the LSI circuit. Thus, in the LSI circuit, the stress is applied to part of the LSI circuit corresponding to the placed pads, whereas the stress is not applied to the remaining part of the LSI circuit. In a stress distribution inside the chip, an expansion amount is different between the chip and an interposer (e.g., the substrate 103 in FIGS. 12 and 13) depending on a temperature, and therefore it is likely that greater stress is applied to an outer circumferential part of the chip.
Examples of influences of stress application on the LSI circuit include a change in characteristics of transistors. Thus, the characteristics of the transistors positioned right below the pads are changed, resulting in non-uniformity of the operation speed of each transistor of the LSI circuit. This influences operation timing of the LSI circuit. As a result, malfunction of the LSI circuit, reduction in yield ratio, etc. occur.
Japanese Unexamined Patent Publication No. 2010-141080 (hereinafter referred to as “Patent Document 1”) discloses a semiconductor device including a semiconductor memory chip which includes an external connection terminal and first and second memory terminals and in which the external connection terminal and the first memory terminal are electrically connected together through a first memory interconnect layer, and a semiconductor logic circuit chip which is smaller than the semiconductor memory chip and which includes, on a principal surface thereof, first and second logic circuit terminals. The semiconductor logic circuit chip is stacked on the semiconductor memory chip such that at least the first memory terminal of the semiconductor memory chip and the first logic circuit terminal of the semiconductor logic circuit chip electrically contact each other.
Moreover, Japanese Unexamined Patent Publication No. 2008-060587 (hereinafter referred to as “Patent Document 2”) discloses the technique by which a dummy terminal is provided on a semiconductor chip and on four corners or a diagonal line of an interposer.